The present invention relates to a bus system and, more particularly, to a technology for controlling the access right of a hardware item connected to a bus, which is effective when applied to, e.g., a semiconductor integrated circuit.
As a technology for preventing a data region from being rewritten by an unauthorized access from a task in an extended memory address space apparatus, there has been known one disclosed in, e.g., Patent Document 1. According to the technology, a data region access right definition table which defines the enabling/disabling of access to a data region for a task (or an interruption process) being executed is provided in a cache. An address arithmetic unit extracts a data region ID from a CPU address inputted from a central processing unit (CPU). A register bank control unit references the foregoing definition table in the cache and judges the access right of the task being executed to the data region from the task ID (or the interruption number of the interruption process) of the task that has been stored in an ID register and from the extracted data region ID mentioned above. When the access is not enabled, a system error judgment is made and, if the access is enabled, the process of converting the foregoing CPU address to an extended address is performed.
There has also been known a technology disclosed in, e.g., Patent Document 2 as a technology for preventing the execution of data transfer to an unauthorized address such as an address to which a memory has not been allocated or an address used for another purpose in performing DMA transfer using a direct memory access controller (DMAC). According to the technology, when the DMA transfer is performed by using the DMAC, data stored in a store region at one address (source address) is sequentially read out and transferred to a store region at the other address (destination address) by referencing an address range used for a data transfer process between the memory and a peripheral circuit. Data indicative of one and the other addresses has been stored in address registers in the DMAC. At this time, a valid address range individually allocated to the memory or the peripheral circuit has been stored preliminarily in a valid address table such that a monitor unit compares the address range indicated by the data used for the transfer process that has been stored in the individual address registers with the address range stored in the valid address table in performing the transfer process and, when the address range indicated by the data used for the transfer process deviates from the valid address range, the transfer process is interrupted.
[Patent Document 1] Japanese Unexamined Patent Publication No. 2001-005726 (FIG. 2)
[Patent Document 2] Japanese Unexamined Patent Publication No. 2001-297054 (FIG. 2)